> Hi guys I badly need your help on how to design for a diagram of 3bit parity generator and 4bit even parity checker. Ple

Hi guys I badly need your help on how to design for a diagram of 3bit parity generator and 4bit even parity checker. Ple

Posted at: 2014-12-18 
Even parity, you want an even number of bits including the parity.

For every XOR you use to test two bits, you will get a 1 if the number of input bits are odd and a 0 if the number of input bits are even.

Call the bits, A, B, C.

Truth table for A XORed with B and the output (RES) XORed with C to create the final parity bit, P.

A B RES C P

0 0 | 0 0 | 0

0 1 | 1 0 | 1

1 0 | 1 0 | 1

1 1 | 0 0 | 0

0 0 | 0 1 | 1

0 1 | 1 1 | 0

1 0 | 1 1 | 0

1 1 | 0 1 | 1

In all cases, the parity bit will make the total number of bits even

The parity checker is just a combination of XOR gates.

A XORed with B, C XORed with P, and the outputs XORed together.

A B RES1

0 0 | 0

0 1 | 1

1 0 | 1

1 1 | 0

C P RES2

0 0 | 0

0 1 | 1

1 0 | 1

1 1 | 0

RES1 RES2 CHECK

0 0 | 0

0 1 | 1

1 0 | 1

1 1 | 0

The end result will produce a 0 if the parity is ok. If you need a 1 output if the parity check is ok, invert the output.

CHECK CHECK'

0 | 1

1 | 0

The end result will produce a 1 if the parity is even.

1. Design a 3-bit even parity generator and a 4 bit even parity checker. Hint: Make a truth table, and from this truth table, obtain the Boolean expression for the circuit, then implement the circuit using logic gates.

Thank you in advance for the the one's who'll help!

God Bless :>